A Hardware-In-The-Loop CI/CD Validation Framework for IoT and Vehicle Embedded Systems Using C# and Azure Devops
DOI:
https://doi.org/10.65150/EP-gjetr/V2E9/2026-10Keywords:
Hardware-in-the-loop (HIL), CI/CD pipelines, Embedded systems validation, IoT firmware testing, A sutomotiveoftware, Azure DevOps, C# orchestration, Cyber-physical systems testingAbstract
Continuous integration and delivery transformed mainstream software engineering, yet embedded development for Internet of Things devices and vehicle systems remains only partially served by it, because the property that matters most, correct behavior of software on real hardware interacting with real signals, is exactly the property that conventional build-and-unit-test pipelines never exercise. Hardware-in-the-loop validation closes that gap in principle, but in most organizations, it lives outside the delivery pipeline, operated manually, scheduled informally, and consulted late, so integration defects that only hardware reveals are discovered at the cost and latency that continuous practices exist to eliminate. This paper proposes a framework that makes hardware-in-the-loop validation a first-class, automated stage of a CI/CD pipeline, specified concretely for C#-based orchestration within Azure DevOps and targeted at embedded software for IoT and vehicle systems. The framework defines a four-ring test architecture, static and unit rings on build agents, software-in-the-loop rings against simulation, and hardware-in-the-loop rings against instrumented device farms, with ring promotion governed by explicit gates; an orchestration layer, implemented as C# services, that manages rig inventory, device provisioning and flashing, test scheduling with priority and quarantine policies, signal-level stimulus and measurement, and artifact capture; and pipeline integration expressed as pipelines-as-code with environment checks, approval gates, and traceable promotion from commit to release candidate. The framework treats the known pathologies of continuous embedded testing, scarce rigs, long test times, flaky hardware, and version skew between software, firmware, and rig configuration, as design inputs with named mechanisms. An evaluation plan measures defect-detection shift, pipeline latency, rig utilization, and flakiness containment. Applications, limitations, and adoption pathways are analyzed.
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Copyright (c) 2026 Kingsley Chinazaekpere Ndupu, Emmanuel Eniola Ajala, Serif Oyindamola Oyesiji, Stanley Nwakamma (Author)
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